1. Field of the Invention
The present invention relates to the field of data processing. More particularly, the invention relates to level shifting circuitry.
2. Description of the Prior Art
Different portions of an integrated circuit may operate at different voltage levels. To convert between signals in one voltage domain and signals in another voltage domain, level shifting circuitry may be used. FIG. 1 of the accompanying drawings shows a typical level shifter comprising two pullup transistors 202, 302 and two pulldown transistors 203, 303. The input signal DATA switches between VDD and ground voltage levels. In response to the input signal, the level shifting circuitry generates an output signal which switches between DVDD and ground voltage levels. In response to a rising edge of the input signal DATA, pulldown transistor 203 pulls node OUTB to ground, which switches on pullup transistor 302, pulling the output signal OUT to DVDD. In contrast, in response to a falling edge of the input signal DATA, the signal DB, which is an inverted version of the input signal, turns on pulldown transistor 303, which pulls the output signal OUT to ground.
A problem arising with the level shifter shown in FIG. 1 is that even though pullup devices 202, 302 are the pullup devices for the output nodes OUT, OUTB, the pullup transistors 202, 302 must be sized so that the pulldown transistors 203, 303 can overcome them when the output nodes OUT, OUTB need to be switched to the ground voltage level. This is particularly a problem when the input voltage domain uses a low VDD level, in which case the threshold voltage of pulldown transistors 203, 303 may be high compared to VDD so that the VDD level of the input signal DATA and the inverse input signal DB barely turns on the pulldown transistors 203, 303. At this point, the level shifter fails because the pulldown transistors 203, 303 can no longer overcome the pullup transistors 202, 302.
Therefore, the level shifter shown in FIG. 1 generally requires the VDD level to be sufficiently high to allow the pulldown transistors 203, 303 to overcome the pullup transistors 202, 302. This limits the extent to which the VDD level in the input voltage domain can be reduced, limiting the amount of power saving that is possible. Therefore, the present technique seeks to provide level shifting circuitry which can address this problem and operate with an input voltage domain having a relatively low upper voltage level VDD.